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2017
Mass production of FeRAMｓ that can operate at temperatures of up to 125℃ started (RAMXEED)

*** Integrated Circuits ***

Around 1987, Ramtron announced FeRAM (Ferroelectric Random Access Memory), a nonvolatile memory using a ferroelectric thin film, which in principle had the potential to achieve high memory density with high-speed operation equivalent to DRAM, and had attracted attention as the ultimate memory. A number of prominent domestic and foreign semiconductor manufacturers entered R&D of FeRAM in the late 1990s and early 2000s. However, FeRAM had many challenges in microfabrication, and the design rule of 130 nm was the limit of miniaturization, making it difficult to achieve high memory density memory. As of 2021, the maximum commercialized FeRAM density is 4 Mb, and manufacturers are limited to a few companies worldwide, including RAMXEED and Infineon.

The write speed of FeRAM is comparable to that of DRAM, about 100 times faster than that of flash memory, and the rewrite tolerance of 1013 times is 100 million times higher than that of flash memory(105times) and it consumes less power [1]. FeRAM, pioneered by Fujitsu in 1999, which was adapted in the contactless IC card Felica in 2006, has beeｎ widely used in applications where data rewriting occurs cumbersomely in real time and for high-speed data backup during emergency power off [2][3][4].

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Table 1   Comparison of semiconductor memory characteristics [1] Table 1 Comparison of semiconductor memory characteristics

FeRAM is suitable for nonvolatile memory for high-speed data logging, such as in-vehicle electronic devices for automated driving. But in-vehicle memory must be capable of operating in a wide temperature range of at least -40℃ to 125℃. The upper operating temperature limit for standard memory is 75℃ to 85℃. In order to raise the upper limit of operating temperature, corresponding technological development is necessary.

FeRAM utilizes the residual polarization of ferroelectric materials. In commercialized FeRAM, lead zirconate titanate (Pb(Zr,Ti)O3: PZT) has been used as a ferroelectric material.

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Ferroelectric memory operation is explained by using the relationship between the amount of ferroelectric polarization and voltage shown in Figure 2. Assuming that the initial state of the ferroelectric material is at a voltage of 0 and the amount of polarization Pr- (“1” is written), if the voltage is increased in the positive direction, the amount of polarization becomes 0 at a voltage of Vc+. As the voltage is further increased, the polarization reverses and the amount of reversed polarization increases. As the voltage is reduced from this state, the amount of polarization becomes Pr+ (writing “0”) at voltage 0, and the amount of polarization becomes 0 at voltage Vc-. The voltage is further decreased in the negative direction, and when the voltage is again increased in the positive direction, the original state (“1”) is restored. The sum of absolute values of Pr- and Pr+ are defined as 2Pr and the sum of absolute values of Vc+ and Vc- are defined as 2Vc, respectively. The larger 2Pr, the greater the ability to retain memory, and the smaller 2Vc, the lower the voltage at which data can be rewritten. Generally, as temperature increases, 2Pr and 2Vc become smaller, making it easier to write, but harder to retain memory [1]. And the leakage current generated also increases [7].

Figure 2 Relationship between the amount of ferroelectric polarization and voltage

Figure 2   Relationship between the amount of ferroelectric polarization and voltage

PZT, which is widely used as a ferroelectric material, is heat treated at high temperatures between 650℃ and 750℃ to crystallize (columnar crystal grains) and develop polarization. During high temperature thermal treatment, the reduction action by hydrogen generated by the catalytic action of the oxidation-resistant noble metal electrode or by hydrogen annealing in the subsequent multilayer metal wiring process causes the oxygen in PZT to be released, resulting in a decrease in polarization and generation of leakage current due to crystal defect. To prevent this phenomenon, various techniques are required to avoid hydrogen and water penetration, such as carefully wrapping the ferroelectric material with a protective film.

The cross-sectional structure of the ferroelectric capacitor (FC) developed by RAMXEED is shown in Figure 3 [8]. Bi doped strontium ruthenate (B-SRO: Bi doped SrRuO3) is inserted into the general FC structure where PZT is sandwiched between an iridium (Ir) bottom electrode and an iridium oxide (IrOx (1<x<2)) top electrode. Due to requires of PZT crystallization at 600℃ or higher, an oxidation-resistant Ir-based electrode is used. In PZT capacitors, it has been found that a small amount of Ir diffusing from the top electrode into the PZT lowers 2Vc and increases 2Pr [10]. However, too much of this Ir diffusion lowers 2Pr conversely. By means of adjusting the thickness of the B-SRO, the amount of Ir diffusion can be controlled to increase the operating margin of FeRAM. B-SRO also suppresses the diffusion of Pb and O (oxygen atoms) from PZT to the top electrode, thereby suppressing leakage current [7][10].

Figure 3 Cross-sectional structure of a ferroelectric capacitor

Figure 3   Cross-sectional structure of a ferroelectric capacitor [8]
(courtesy of RAMXEED Corporation)

RAMXEED's FeRAM memory adopts a COB (capacitor-over-bit line) structure. FCs have been spread on the entire chip surface as shown in Figures 4 and 5. A triple protection structure is adopted to prevent PZT from being reduced by water or hydrogen during the manufacturing process, resulting in a decrease in polarization residual [11].The triple protection structure consists of a capacitor wrapper consisting of a metal layer at the bottom of the capacitor and an insulating film covering the top and sides of the capacitor, a protective box surrounding the capacitor area with two SiN layers, a capacitor row (inner wall) and two metal plates, and a protective outer wall formed by the outer side capacitor array..

Figure 4 Planar Schematic of Memory Cell Array

Figure 4   Planar Schematic of Memory Cell Array
(Prepared by the Japan Semiconductor History Museum based on Ref. (11))

Figure 5 Cross-sectional schematic of the cell array edge shown at X-X' in Figure 4

Figure 5   Cross-sectional schematic of the cell array edge shown at X-X' in Figure 4
(Prepared by the Japan Semiconductor History Museum with reference to reference [11])

As the temperature rises, the residual polarization of PZT decreases and the leakage current increases, making it difficult to retain memory. RAMXEED (formerly Fujitsu Semiconductor Memory Solutions) has succeeded in improving the crystallinity of PZT and reducing defects by optimizing the deposition temperature and pressure of the metalorganic vapor deposition (MOCVD) process used to deposit PZT, as well as the annealing conditions of the deposited film to generate polarization, in addition to structural improvements in ferroelectric capacitors. A PZT film with low leakage current and sufficient residual polarization even at 125℃ was realized.

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RAMXEED increased the annealing temperature in an oxygen atmosphere of PZT deposited by metalorganic vapor deposition (MOCVD) from 600℃ to 700℃ to enhance the crystallinity of PZT. This improved 2Pr measured at 125℃ by about 2 μC/cm2 (Figure 6(a)). However, 2Vc measured at room temperature was about 0.08 V larger (Figure 6(b)). In order to reduce the 2Vc, the thickness of PZT was reduced from 85 nm to 75 nm. The aim was to increase the effective electric field by making ferroelectricity thinner. Furthermore, the thickness of B-SRO, which was previously set at 1 nm, was now set at 2 nm or more to provide sufficient margin for uniformity within the wafer plane. Through these measures, 2Vc was finally reduced by about 0.4V (Figures 7(a) and 7(b)). The leakage current was reduced by lowering the MOCVD pressure from 270 Pa to 150 Pa to suppress gas phase reactions in the deposition chamber and reduce defects in the PZT. Figure 8 shows the leakage current density of FC measured at 125℃. The leakage current has been significantly suppressed.

Figure 6(a) 2Pr (measured at 125℃) when the annealing temperature after ferroelectric deposition is 700℃ instead of the conventional 600℃

Figure 6(a)   2Pr (measured at 125℃) when the annealing temperature after ferroelectric deposition is 700℃ instead of the conventional 600℃
(courtesy of RAMXEED Corporation)

Figure 6(b) 2Vc (measured at room temperature) when the annealing temperature after ferroelectric film deposition is 700℃ instead of the conventional 600℃

Figure 6(b)   2Vc (measured at room temperature) when the annealing temperature after ferroelectric film deposition is 700℃ instead of the conventional 600℃
(Courtesy of RAMXEED Corporation)

Figure 7(a) 2Vc (measured at room temperature) when the ferroelectric thickness is 75 nm instead of the conventional 85 nm

Figure 7(a)   2Vc (measured at room temperature) when the ferroelectric thickness is 75 nm instead of the conventional 85 nm
(Courtesy of RAMXEED Corporation)

Figure 7(b) 2Vc (measured at room temperature) when the thickness of B-SRO is increased from the conventional 1 nm to 2 nm

Figure 7(b)   2Vc (measured at room temperature) when the thickness of B-SRO is increased from the conventional 1 nm to 2 nm
(Courtesy of RAMXEED Corporation)

Figure 8 Leakage current density vs. voltage when ferroelectric film deposition pressure is 150 Pa instead of the conventional 270 Pa (measured at 125℃)

Figure 8   Leakage current density vs. voltage when ferroelectric film deposition pressure is 150 Pa instead of the conventional 270 Pa (measured at 125℃)
(courtesy of RAMXEED Corporation)

RAMXEED has successfully mass-produced 256kbFeRAM operating at 125℃ in 2017 and 4MbFeRAM operating at 125℃ in 2021 by using this technology, (5) (Figure 1). The 4MbFeRAM was manufactured by using a 180nm 6-layer metal interconnect CMOS process, and the memory unit adopts a 2T2C (two transistors and two capacitors) configuration with highly reliable data retention characteristics.

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FeRAM has a circuit configuration similar to that of DRAM, with the DRAM's paraelectric capacitor replaced by a ferroelectric capacitor (FC), as shown in Figure 9. In FeRAM, data is written and read out by driving the plate (PL) and bit line (BL). An examples of FC polarization directions and stored values is shown in the upper left corner of Figure 9. In the “1” write, PL is grounded, voltage is applied to BL, and the transistor (Tr) is turned on to polarize the ferroelectric upward. In a “0” write, PL is given a voltage and BL is grounded. In the readout, a voltage is applied to PL, Tr is turned on, and a voltage is applied to FC to read the potential rise of BL, which is in a floating state. The “0” readout, which does not invert the ferroelectric polarization, has less charge flowing into the BL than the “1” readout, which inverts the ferroelectric polarization, so the increase in voltage is smaller. This is used to discriminate between “1” and “0” readouts.

Figure 9 FeRAM circuit configuration

Figure 9   FeRAM circuit configuration
(courtesy of RAMXEED Corporation)

This memory can operate in a wide range of 1.8 V to 3.6 V, can be rewritten 1013 times (10 trillion times), and can be used at temperatures up to 125℃. It complies to the high-quality standard AEC-Q100 Grade 1 and is ideal for automotive advanced driver assistance systems (ADAS) and high-performance industrial robots.

Figure 1 Appearance of 4 Mb FeRAM for automotive applications

Figure 1   Appearance of 4 Mb FeRAM for automotive applications [5]
(courtesy of RAMXEED Corporation)

[Supplementary information]

The ferroelectric PZT used in commercialized FeRAM has a size effect, and the amount of polarization decreases rapidly when the thickness falls below 100 nm. For this reason, it is difficult to miniaturize below the design rule of 180 to 130 nm. It was found that Hf-based oxides used in the HKMG process became ferroelectric under certain crystallization conditions and maintained ferroelectric properties even at thicknesses of 10 nm or less in 2011. Hf-based oxides can maintain ferroelectricity with low leakage current even when thinned to 10 nm or less, and have strong resistance to hydrogen, enabling miniaturization of memory devices. In order to realize highly integrated nonvolatile memory, research and development of 1T1C FeRAM using HZO (HfZrO4), 1T0C FeFETs in which HZO is inserted into the gate insulator of an FET, and ferroelectric tunnel junction (FTJ) memory has become active. Ferroelectric materials such as AlScN and GaScN have also been discovered that exhibit polarization at thicknesses of only a few nm, and memory devices are entering a new generation [6].

[Reference]

  1. RAMXEED Corporation website, "Learn more about FeRAM" (Japanese)
    https://www.ramxeed.com/jp/tech-column/
  2. T. Yamazaki, K. Inoue, H. Miyazawa, M. Nakamura, N. Sashida, R. Satomi, A. Kerry, Y. Katoh, H. Noshiro, K. Takai, R. Shinohara, C. Ohno, N. Nakajima, Y. Furumura, and K. Kawamura, "Advanced 0.5μm FRAM Device Technology with Full Compatibility of Half-Micron CMOS Logic device," Proc. Int. Electron Devices Meeting, p. 613－616. (1997), DOI: 10.1109/IEDM.1997.650459.
  3. Semiconductor History of Japan, Integrated Circuits, "2001: Release of LSI with embedded FeRAM for IC cards (Fujitsu and Matsushita)"
    https://www.shmj.or.jp/english/pdf/ic/exhibi714E.pdf
  4. Fujitsu Limited press release, "FRAM-based LSI adopted for FeliCa IC cards", (November 7, 2006) (Japanese)
  5. RAMXEED Corporation Press Release, "Automotive Grade Compliant 4 Mbit FeRAM with 125℃ Operation Begins Mass Production," (July 6, 2021) (Japanese)
    https://www.ramxeed.com/jp/news-and-updates/3375/

[Related Documents]

  1. Masashi Kobayashi, ”Current status and challenges of emerging ferroelectric-HfO2 based memory devices”, OYO BUTSURI, vol. 89, no.6, pp.314-320, (2020)
  2. W. Wang, K. Takai, K. Nakamura, M. Oikawa, S. Ozawa, K. Nagai, S. Mihara, Y. Hikosaka, H. Saito, M. Kojima, T. Eshita, K. Nomura, H. Yamaguchi "A new electrode structure of IrOx/Bi-doped SrRuO3 for highly reliable La-doped Pb (Zr, Ti)O3-based ferroelectric memories," 22nd Int. Symp. INFOTEH-JAHORINA (INFOTEH) (March, 2023), DOI:10.1109/infoteh57020.2023.
  3. Wensheng Wang, Japan Patent 4983172, 5593935
  4. K. Nomura, W. Wang, K. Nakamura, T. Eshita, K, Takai, S, Ozawa, H. Yamaguchi, S. Mihara, Y. Hikosaka, H. Saito, Y. Kataoka, and M. Kojima, "Reconstruction of IrO2/(Pb, La)(Zr, Ti)O3 (PLZT) interface by optimization of postdeposition annealing and sputtering conditions", J. Appl. Phys., vol. 126, p. 074105 (2019), DOI: 10.1063/1.5091501.
  5. W. Wang, K. Takai, T. Eshita, M. Nakabayashi, K. Nakamura, M. Oikawa, N. Sato, K. Suezawa, Y. Okita, S. Ozawa, S. Mihara, Y. Hikosaka, H. Saito, and K. Nagai, "Development of a High-Endurance Ferroelectric Capacitor for FeRAM in Automotive and Industrial Applications," Trans. Electron Devices. (early access), doi: 10.1109/ted.2024.3514579.
  6. H. Saito, T. Sugimachi, K. Nakamura, S. Ozawa, N. Sashida, S. Mihara, Y. Hikosaka, W. Wang, T. Hori, K. Takai, M. Nakazawa, N. Kosugi, M. Okuda, M. Hamada, S. Kawashima, T. Eshita, and M. Matsumiya, “A triple-protection structured COB FRAM with 1.2-V operation and 1017-cycle endurance, ” 2015 IEEE International Memory Workshop (IME) (May, 2015), DOI:10.1109/IMW.2015.7150275.
  7. T. Eshita, W. Wang, and Y. Hikosaka　"Ferroelectric Memory," Elsevier Science, Encyclopedia of Materials: Electronics pp. 218-240 (March 2023), DOI: 10.1016/B978-0-12-819728-8.00042-5.
  8. W. Wang, K. Nakamura, M. Nakabayashi, T. Eshita, K. Takai, K. Suezawa, M. Oikawa, N. Sato, S. Ozawa, S. Mihara, Y. Hikosaka, H. Saito, and K. Nagai, "A ferroelectric capacitor with an asymmetric double-layered ferroelectric structure comprising a liquid-delivery MOCVD Pb(Zr, Ti)O3 layer and a sputter-deposited La-doped Pb(Zr, Ti)O3 for highly reliable FeRAM," Appl. Phys. Lett. 125, 192901. 2024, doi: 10.1063/5.0230646.
  9. W. Wang, T. Eshita, K. Takai, S. Amari, K. Nakamura, M. Oikawa, N. Sato, S. Ozawa, M. Nakabayashi, S. Mihara, Y. Hikosaka, H. Saito, K. Inoue, and K. Nagai, "Highly Reliable 4 Mb FeRAM Using a Newly Developed PLZT Capacitor With a Bi-Doped SRO Interlayer." IEEE Electron Device Lett.45, pp 2126-2129,2024, doi: 10.1109/led.2024.3459044.
  10. W. Wang, T. Eshita, K. Takai, K. Nomura, H. Yamaguchi, K. Nakamura, S. Ozawa, K. Nagai, J. Watanabe, S. Mihara, Y. Hikosaka, H. Saito, and M. Kojima, "An improvement of low temperature characteristics of an La-doped Pb(Zr, Ti)O3 capacitor," Jpn. J. Appl. Phys. vol. 61, (2022), DOI: 10.1109/infoteh57020.2023.
  11. W. Wang, K. Nakamura, T. Eshita, K. Nomura, K. Takai, H. Yamaguchi, S. Mihara, Y. Hikosaka, H. Saito, and M. Kojima, "Ferroelectric capacitor with an asymmetric double-layer PLZT structure for FRAM, " Appl. Phys. Lett. vol. 120, p. 102901 (2022), DOI: 10.1063/5.0083645.
  12. W. Wang, K. Nomura, K. Nakamura, T. Eshita, S. Ozawa, H. Yamaguchi, K. Takai, J. Watanabe, S. Mihara, Y. Hikosaka, H. Saito, Y. Kataoka, and M. Kojima, "Ferroelectric random access memory with high electric properties and high production yield realized by employing an AlOx underlying layer of Pt bottom electrode for a La-doped lead zirconate titanate capacitor," Jpn. J. Appl. Phys. vol. 58, p. 016503 (2019), DOI: 10.7567/1347-4065/aae899.
  13. K. Nomura, W. Wang, H. Yamaguchi, K. Nakamura, T. Eshita, S. Ozawa, K. Takai, S. Mihara, Y. Hikosaka, M. Hamada, M. Kojima, and Y. Kataoka, "Improvement of ferroelectric random access memory manufacturing margin by employing Pt/AlOx bottom electrode for the La-doped Pb(Zr, Ti)O3 ferroelectric capacitor”, Jpn. J. Appl. Phys. vol. 57 p. 11UF01 (2018), DOI: 10.7567/jjap.57.11uf01.
  14. K. Nomura, W. Wang, H. Yamaguchi, K. Nakamura, T. Eshita, S. Ozawa, K. Takai, S. Mihara, Y. Hikosaka, M. Hamada, M. Kojima, Y. Kataoka, "Effect of Pt/AlOx Bottom Electrode on the Manufacturing Process Margin Improvement of La-Doped Pb(Zr; Ti)O3 Thin Films," 2018 ISAF-FMA-AMF-AMEC-PFM (IFAAP) Joint Conf. (2018).
  15. W. Wang, K. Nomura, H. Yamaguchi, K. Nakamura, T. Eshita, S. Ozawa, K. Takai, S. Mihara, Y. Hikosaka, M. Hamada, and Y. Kataoka "Control of La-doped Pb(Zr,Ti)O3 crystalline orientation and its influence on the properties of ferroelectric random access memory," Jpn. J. Appl. Phys. vol. 56, p.10PF14 (2017), DOI: doi.org/10.7567/jjap.56.10pf14.
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Ver.001: 2025/8/12